IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
IEEE Computer Architecture Letters是一个经过严格同行评审的论坛，旨在发布单处理器和多处理器计算机系统、计算机体系结构、微体系结构、工作负载特征、性能评估和模拟技术以及功耗感知计算等领域的早期、高影响力成果。欢迎您就计算机体系结构的任何主题提交意见，特别是但不限于：微处理器和多处理器系统、微体系结构和ILP处理器、工作负载表征、性能评估和模拟技术、编译器-硬件和操作系统-硬件交互、互连体系结构、存储器和高速缓存系统、体系结构级的功率和热问题、I/O体系结构和技术、先前发表结果的独立验证、不成功技术的分析域专用处理器体系结构（例如，嵌入式、图形、网络等），实时和高可用性架构、可重构系统。
A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2892151
Spatial Correlation and Value Prediction in Convolutional Neural Networks
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2018.2890236
PPT-GPU: Scalable GPU Performance Modeling
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2904497
Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2935049
A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2951507
RTSim: A Cycle-Accurate Simulator for Racetrack Memories
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2899306
Orbital Edge Computing: Machine Inference in Space
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2907539
SMT-SA: Simultaneous Multithreading in Systolic Arrays
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2924007
Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2018.2889042
PIMSim: A Flexible and Detailed Processing-in-Memory Simulator
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2018.2885752
A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2909870
Design Space Exploration of Memory Controller Placement in Throughput Processors with Deep Learning
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2905587
Coordinated DVFS and Precision Control for Deep Neural Networks
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2942020
Detect DRAM Disturbance Error by Using Disturbance Bin Counters
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2897299
Locality-Aware GPU Register File
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2959298
Scalable LLVM-Based Accelerator Modeling in gem5
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2893932
Isolating Speculative Data to Prevent Transient Execution Attacks
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2916328
NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2898196
Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2910521
Asymmetric Resilience for Accelerator-Rich Systems
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2917898
Tuning Performance via Metrics with Expectations
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2916408
Shimmer: Implementing a Heterogeneous-Reliability DRAM Framework on a Commodity Server
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2893189
Modeling Emerging Memory-Divergent GPU Applications
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2923618
Massively Parallel Server Processors
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2911287
Dark Wires and the Opportunities for Reconfigurable Logic
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2909867
Precise Runahead Execution
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2910518
HAD-TWL: Hot Address Detection-Based Wear Leveling for Phase-Change Memory Systems with Low Latency
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2929393
Rusty: Runtime System Predictability Leveraging LSTM Neural Networks
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2924622
Are Crossbar Memories Secure? New Security Vulnerabilities in Crossbar Memories
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2952111
A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2908374
Code Layout Optimization for Near-Ideal Instruction Cache
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2924429
Performance and Fairness Improvement on CMPs Considering Bandwidth and Cache Utilization
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2944810
Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2955119
Hybrid Remote Access Protocol
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2896116
Power Profiling of Modern Die-Stacked Memory
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2941715
SVSoC: Speculative Vision Systems-on-a-Chip
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2903241
DAEGEN: A Modular Compiler for Exploring Decoupled Spatial Accelerators
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2955456
ARCE: Towards Code Pointer Integrity on Embedded Processors Using Architecture-Assisted Run-Time Metadata Management
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2935445
Exploiting OS-Level Memory Offlining for DRAM Power Management
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2942914
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2952592
A Case For Asymmetric Processing in Memory
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2894800
Speeding up Collective Communications Through Inter-GPU Re-Routing
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2933842
LOOG: Improving GPU Efficiency With Light-Weight Out-Of-Order Execution
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2951161
Performance Modeling and Bottleneck Analysis of EDGE Processors Using Dependence Graphs
来源期刊：IEEE Computer Architecture LettersDOI：10.1109/LCA.2019.2911514
